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dingshiqi188
- VHDL--定时器设计-Design of a Timer Based on CPLD
shuzizhong_VHDL
- 用VHDL语言写了数字钟程序，并用数码管显示，经过硬件调试可行-timer clock
Exp3_Timer
- 用VHDL在SOPC试验箱中实现定时器，用ＶＨＤＬ硬件描述语言实现处理器CPU-Use VHDL to implement the timer in SOPC chamber, with the VHDL hardware descr iption language processor CPU
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
RS232_FIR
- Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: a
30daojishi
- 30秒倒计时器，基于VHDL语言。具有循环计时功能，-30 seconds countdown timer, based on the VHDL language. With a cycle time function,
siluqiangdaqi
- 通过VHDL程序设计一个4人参加的智力竞赛抢答计时器，当有某一参赛者首先按下抢答开关时，相应显示灯亮并伴有声响，此时抢答器不再接受其他输入信号。 电路具有回答问题时间控制功能。要求回答问题时间小于等于100s(显示为0~99)，时间显示采用倒计时方式。当达到限定时间时，发出声响以示警告。 -VHDL programming by a 4 quiz participants answer in timer, when a participant first press the answe
clock
- 用VHDL实现多功能数字钟 闹铃 计时 动显 报时等-VHDL realization of multi-functional digital clock with alarm timer was timekeeping and other fixed
digital-electronic-clock
- 基于VHDL的数字电子时钟的设计 实现计时，秒表，闹钟功能-VHDL-based design implementation digital electronic clock timer, stopwatch, alarm clock function
ise8tut
- 定时器的VHDL程序,包括几个文件，分别使用了集中顶事方式.-timer program using vhdl
VHDLBasicExperimentSJTU
- 上海交大几个基础VHDL 实验的代码,包括分频器，计数器，七段计数器，状态机，锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
clock1
- VHDL语言实现多功能数字钟设计：(1) 计时功能：这是本计时器设计的基本功能，每隔一分钟计时一次，并在显示屏上显示当前时间。 (2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出蜂鸣声。 (3) 设置新的计时器时间：用户用数字键‘0’～‘9’输入新的时间，然后按 "TIME"键确认。 (4) 设置新的闹钟时间：用户用数字键“0”～“9”输入新的时间，然后按“ALARM”键确认。过程与(3)类似。 (5) 显示所设置的闹钟时间：在正常计时显示状态下，用户直接
sequential_design_Timer
- Document on sequential design Timer in VHDL for starters.
trafficlight
- 基于VHDL的十字路口交通灯控制系统设计与实现,定时器模块由25S、5S、20S三个定时器组成，分别确定相应信号灯亮的时间。三个定时器采用以秒脉冲为时钟的计数器实现。eg、ey、er分别是三个定时器的工作使能信号，tm25、tm5、tm20是三个定时器的计数结束指示信号。 控制模块是对系统工作状态的转换进行控制，根据交通规则可得系统状态转换情况。ar、ay、ag br、by、bg分别表示由控制器输出的A道和B道的红、黄、绿信号灯亮的时间；eg、ey、er分别表示由控制器输出的控制25S、5S
cntm60
- VHDL实现的60s计时器,用于时钟控制电路，实现计时。-the 60 seconds timer based on VHDL is used to controling the electronic circuit of timer.
wtut_vhd
- spartan 3E 1600开发板的秒表计时器源程序，VHDL语言-source code of timer on spartan 3E1600 development board in VHDL
a_vhdl_8253_timer_latest[1].tar
- 因特尔8254 计时器的vhdl语言实现-a VHDL version of the Intel 8254 timer
VVHDL_32bit_tH
- VHDL写的32位计数，两个四位共阳数码管输出串口输出+数码码管显示的计时器程序每次停止后串口输出。，已通过测试。 -VHDL written 32 count, two four sun digital serial output tube output serial output the+ digital code to display the timer program each stop. , Has been tested.
div50m
- 用VHDL代码编写的50分频器,已经经过Quarter仿真，证明正确，可用于计时器中-50 divider using VHDL code has After Quarter simulation, proved correct, can be used in the timer
dingshijishu.vhd
- 基于VHDL语言环境的定时计数程序，可进行简单的定时计数，供大家改进开发。-Simple timer count timer count program based on the VHDL language environment for improved development.